Display panels typically require various driver circuits for proper operation. Such circuits include source driver circuits, gate driver circuits and the like. The integrated circuits associated with such display drivers typically include timing generators, DC-DC converters, amplifiers, signal processors, CPUs, memories and the like. Among these circuits the timing controller is responsible for providing control signals to the driver circuits, including such control signals as horizontal start (HST), horizontal clock (HCK), vertical start (VST), vertical clock (VCK) and the like. Such a typical control circuit and associated display is shown in FIG. 1.
For such displays, a timing controller typically comprises two counters; namely, a dot counter (H counter) for the horizontal direction and a line counter (V counter) for the vertical direction. Schematically the time controller is shown in FIG. 10. The number of binary digits required for these counters is typically determined by the pixel resolution of the associated display. Thus, for example, for a QVGA display comprising 240 pixels in the horizontal direction and 320 pixels in the vertical direction, the horizontal direction would require a dot counter that could count to a number greater than 240 and therefore would require at least eight binary digits (that is 28=256>240). In fact, depending upon the required length of time for horizontal blanking (known as horizontal blanking time), the horizontal count time could be an additional 10%, which for a 240 pixel width would add 24 pixels, making the total horizontal count equal to 264. In such a case, nine binary digits are required (29=512>264) and the counter repetitively counts from 0 to 263. Such a counter is shown in FIG. 2.
As seen in FIG. 1, a display panel 10 known in the art typically includes a timing controller 12, a gate driver 14, a data driver 16 and a display area 18, wherein the display area has a horizontal dimension of a number of pixels and a vertical dimension of a number of lines, where each line contains a set number of pixels. Thus, in a QVGA-type display, the display area has 240 pixels for each horizontal line and 320 vertical lines, for a total of 76,800 pixels.
As is known in the art, a control signal is generated by the timing controller 12 for controlling the data driver which, in conjunction with the gate driver and its associated control signal, provides for controlled activation or deactivation of each pixel in the display area. Thus, in the horizontal direction for a QVGA-type display area, a pixel (or dot) counter is required that can count the 240 pixels of the display, plus an additional amount of time equal to approximately 10% of the horizontal pixel resolution for purposes of horizontal blanking. Thus, in a typical situation where the blanking time is 10% of the horizontal resolution, the dot counter needs to be able to count to 240 plus 0.1×240, which is equal to 264. FIG. 2 shows a prior art counter comprising nine binary (two-bit) counters 21 which can count from 0 to 512 (29=512). For the horizontal display of a QVGA display with a 10% blanking time, this counter typically counts from 0 to 263 based upon the output C0-C8. As shown in FIG. 2, the counter has nine flip-flops 21. FIGS. 3a-3d show exemplary timing diagrams for the horizontal timing. The output C0 is used to generate the horizontal clock (HCK) signal as shown in FIG. 3c. When the number of clock signals (DCLK) reaches 255, a horizontal start signal (HST) is activated, as shown in FIG. 3d. As can be seen in FIG. 3c, the HCK signal changes state for each complete clock signal and is triggered by the C0 output of binary counter #1. The HST signal is generated when the clock signal (DCLK) reaches a particular value as shown in FIG. 3d. In the present example where the horizontal resolution is 240, the horizontal start signal is generated when the clock signal has had 255 cycles.
As it is known in the art, it is required to use an output generator, which is operatively connected to the 9-bit counter to generate the HST signal based on the output of the 9-bit counter. Furthermore, the 9-bit counter has to be reset when its output reaches 264. A typical output generation scheme for generating the HST and HCK signals from the DCLK and Hsync signals is shown in FIG. 4.
In the vertical direction for a QVGA display, there are 320 lines and thus a nine digit binary counter is required (29>320). Such a counter is shown in FIG. 5. As shown, the counter has nine flip-flops 21. Again, if vertical blanking time is included, such blanking time is typically approximately 10% of the total number of lines, and thus the total number of counts required to be counted in the vertical direction is equal to 320+32=352 and thus the counter would count repetitively from 0 to 351, as determined by the counter outputs N0-N8. FIGS. 6a-6d show exemplary timing diagrams for the vertical timing. As shown, the output N0 from the first binary counter (1) shown in FIG. 5 is used to generate the vertical clock (VCK) signal as shown in FIG. 6c. This horizontal sync signal (Hsync) counts up to 351 and is used for generating a vertical start signal (VST) when the count reaches 339, as shown in FIG. 6d. It is seen that the vertical clock signal (VCK) changes state for each cycle of the horizontal sync signal (Hsync) and that the vertical sync signal changes state when the 330th line is generated while the vertical start signal is generated during the vertical blanking time and, in the example shown in FIG. 6d, when the 339th line is generated during vertical blanking (vertical blanking is between the 304st and the 340nd line). As with the dot counter in the horizontal direction, the line counter in the vertical direction also needs an output generator to generate the VST signal and to reset the line counter when the line counter reaches 352. A typical output generation scheme for generating the VST and VCK signals from the Hsync and Vsync signals is shown in FIG. 7.
As seen in FIG. 8, for a QVGA display the horizontal start signal is typically generated at the 255th count where the counter counts from 0 to 263 and therefore a nine stage binary counter as shown in FIG. 4 is required in a conventional design. Similarly, the vertical start signal is typically generated at the 339th count where the counter counts from 0 to 351 and therefore a nine stage binary counter as shown in FIG. 7 is required.
In view of the foregoing, it can be seen that in general a timing controller for use in a display panel typically requires a full counter for both the horizontal pixel count and the vertical line count, wherein these counters respectively activate the generation of a horizontal start signal (HST) and a vertical start signal (VST). Thus, in the display discussed above, the horizontal start signal (HST) is generated when the count reaches 255 and the vertical start signal (VST) is generated when the vertical line count reaches 339.